Power Modeling and Reduction of VLIW Processors

In this paper, we first present a cycle-accurate power simulator based on the IMPACT toolset. This simulator allows the designer to evaluate both VLIW compiler and microarchitecture innovations for power reduction. Using this simulator, we then develop and compare the following techniques with a bounded performance loss of 1% compared to the case without any dynamic throttling: (i) clock ramping with hardware-based prescan (CRHP), and (ii) clock ramping with compiler-based prediction (CRCP). Experiments using SPEC2000 floating point benchmarks show that the power consumed by floating point units can be reduced by up to 31% and 37%, in CRHP and CRCP respectively.